In the data processing arts, it has been a consistent goal to achieve faster and faster computing rates. In the development of hardware, circuits have been developed which operate at substantially faster rates than many of the main memory devices. It was recognized that the speed at which data processing operations could be completed were often limited by the cycle time of the main memory. To achieve faster computing rates, it was recognized that through the use of a relatively high speed, low capacity buffer storage device, the effective computing rates could approach that of the computing circuitry, rather than being limited by the cycle time of the main memory. The high speed buffer operates intermediate the data processor and the main memory, and when properly implemented, causes the rate of access to the main memory to appear to approach the speed of the buffer.
The storage interface unit described in U.S. Pat. No. 3,967,247, issued to Andersen, et al., describes a storage interface adapted to serve as a high speed buffer between plural requestor units and a relatively lower speed main memory in a data processing system. The storage interface unit described therein improves on the so-called "cache" buffers implemented in various IBM Computer Systems, and described in various articles identified therein.
In systems utilizing such a high speed buffer memory, it is customary for one or more processor units and one or more input-output units to be adapted to receive instructions and operands, hereinafter collectively referred to as "data" from main memory and to store data in main memory only through the use of the high speed buffer memory. Utilizing the probability that reference to a specific data word will lead to further references to data words in a relatively close proximity of storage addresses, the set-associative memories were developed. When a data word is referenced and it is not determined to be stored in the buffer, a data block comprised of a plurality of data words is transferred from the main memory to the buffer memory. The block of data words thus transferred becomes one of several available blocks of data words resident in the buffer memory. These blocks of data words as requested from main memory, remain resident in the buffer memory until displaced by other blocks of data words called from the main memory. The replacement of blocks of data words is accomplished in the prior art by establishing an aging of reference control for each block such that when block replacement is required the block that has been least referenced is selected for replacement. The U.S. Pat. No. 3,967,247, to Andersen et al., previously mentioned, describes such an aging and block replacement system. A further improved aging and block replacement system is described in the U.S. Pat. No. 4,168,541, to DeKarske, and provides for selection of paired least recently used blocks for replacement.
It is well known and common for data processing systems to utilize instruction words and operands, that is, data words, of a predetermined number of bit positions. In set associative memory systems, a predetermined number of data words comprise a block of data, and a predetermined number of blocks of data comprise a set. As mentioned, it is also common to transfer an entire block of data words to the buffer when one of the data words within the block is referenced. A data processor that utilizes two data words at a time encounter a slow down in data processing rates in prior art systems since it would be normally required to have at least two buffer memory cycles to provide the two data words for the processor. A special problem occurs for data processors having the need for utilizing two data words when the two data words are stored at addresses that require a block boundary crossing for the successive data words. The buffer memory of this invention addresses that problem and provides a system for accessing two data words simultaneously when the two data words are in blocks of data words that are resident in the buffer memory. The simultaneous accessing is possible even though the two data words may be resident in two separate blocks of data words. The simultaneous accessing of two data words results in the computing rates being advanced, and effectively reduces the buffer memory cycle time by half.